1. Field of the Invention
The present invention generally relates to sequential logic circuits and, more particularly, to a sequential logic circuit which includes state holding (or "hold") circuits.
2. Description of the Prior Art
Digital logic circuits are categorized as being either a combination logic circuit or a sequential logic circuit. The combination logic circuit generates an output signal which is defined by only the current state of an input signal. The sequential logic circuit generates an output signal which is defined by not only the current state of the input signal but also the previous state thereof. A basic circuit necessary to configure the sequential logic circuit is composed of a latch circuit and a flip-flop. A flip-flop can be formed by two latch circuits.
The flip-flop is categorized as being either a master-slave type flip-flop or an edge triggered type flip-flop. The master-slave type flip-flop is formed with a combination of two latch circuits. The edge triggered type flip-flop inputs an input signal only when a clock signal changes. Generally, it is easy to use the edge triggered type flip-flop, as compared with the master-slave type flip-flop, because the edge triggered flip-flop can be used in a relaxed condition as compared with the master-slave type flip-flop.
Normally, it is necessary to use a large number of normal bipolar transistors in order to configure the edge triggered type flip-flop by using latch circuits and gate circuits. However, it is disadvantageous to use a large number of bipolar transistors in light of integration density and operation speed considerations.
As is well known, an element having a hysteresis characteristic is capable of holding the state of a signal. In principle, a single transistor having a hysteresis characteristic has the inherent function of holding the state of a signal. However, it is impossible to form the sequential logic circuit by simply connecting transistors having hysteresis characteristics without taking into account a clock signal control procedure and an arrangement for outputting an output signal.